1. Field of the Invention
The present invention relates to a semiconductor memory device comprising a bit line-equalizing circuit which charges a pair of bit lines to predetermined potential levels and equalizes the potentials of the bit lines to each other before data is read out from a memory cell.
2. Description of the Related Art
In a dynamic random access memory (DRAM), an equalizing operation is performed before data is read out from a memory cell. The equalizing operation is an operation for charging a pair of bit lines to predetermined potential levels and then equalizing the potential levels to each other. In an ordinary case, the equalizing operation is performed by means of a bit line-equalizing circuit made up of N-channel MOS transistors.
FIG. 1 is a circuit diagram showing the peripheral circuit configuration of a bit line-equalizing circuit employed in a conventional DRAM. (The bit line-equalizing circuit will be hereinafter referred to simply as an "equalizing circuit".) Referring to FIG. 1, an equalizing circuit 14 is made up of three N-channel MOS transistors 11, 12 and 13 and is connected between a pair of bit lines BL and BL. A sense amplifier circuit 15 for detecting data is also connected to the bit lines.
In the equalizing circuit 14, two MOS transistors 11 and 12 are turned on in response to an equalization control signal .phi.EQL, and bit lines BL and BL are pre-charged in accordance with a pre-charging potential VBL. In response to the equalization control signal .phi.EQL, MOS transistor 13 is also turned on. Since the bit lines BL and BL are short-circuited to each other by the ON-state MOS transistor 13, the potentials of the bit lines BL and BL are equalized to each other. After the equalizing circuit 14 sets the potential of the bit lines in this manner, data is read out from a memory cell (not shown). The potential difference which is produced between the bit lines BL and BL when the data is read out is amplified by the sense amplifier circuit 15, so as to detect the data.
In the conventional art, a signal whose level is equal to that of an externally-applied power supply voltage is used as the equalization control signal .phi.EQL supplied to the equalizing circuit 14. Alternatively, a signal whose level is temporarily raised by a known boot-strap circuit up to a level higher than that of the externally-applied power supply voltage is used as the equalization control signal .phi.EQL. The reason why the voltage level of the equalization control signal .phi.EQL must be raised by means of the boot-strap circuit is that, if that voltage level is low, a potential difference is produced between the source and drain of each of the N-channel MOS transistors 11, 12 and 13, and this potential difference does not permit the bit line to be pre-charged to a predetermined potential level VBL.
FIG. 2 is a circuit diagram snowing the peripheral circuit configuration of an equalizing circuit of another conventional DRAM. This DRAM is a so-called shared sense amplifier type wherein a sense amplifier circuit 15 is shared by two bit line pairs (BL1, BL1) and (BL2, BL2). In this type of DRAM, switch circuits 18a and 18b are formed between the bit line pairs and the sense amplifier circuit 15, so as to disconnect the bit line pairs from the sense amplifier circuit 15. Each of the switch circuits 18a aid 18b is made up of two N-channel MOS transistors 19 and 20, and the gates of these MOS transistors 19 and 23 are controlled by switch control signals .phi.T1 and .phi.T2.
The switch circuits 18a and 18b selectively operate when the potential difference between the paired bit lines is amplified by the sense amplifier circuit 15 for data detection. When the potential difference between bit line pair BL1 and BL1 is amplified, the two MOS transistors 19 and 20 of switch circuit 18a are turned on by switch control signal .phi.T1. Likewise, when the potential difference between bit line pair BL2 and BL2 is amplified, the two MOS transistors 19 and 20 of switch circuit 18b are turned on by switch control signal .phi.T2.
In the DRAM depicted in FIG. 2, either signals whose levels are the same as that of an externally-applied power supply voltage or signals whose levels are temporarily raised to be higher than the level of the externally-applied power supply voltage by means of a known boot-strap circuit, are used not only as signals .phi.EQL1 and .phi.EQL2 but also as signals .phi.T1 and .phi.T2. The reason is that signals .phi.T1 and .phi.T2 must be high-level voltages when the MOS transistors 19 and 20 of switch circuits 18a and 18b are turned on. If signals .phi.T1 and .phi.T2 are not high-level voltages then, a potential difference is produced between the source and drain of each of MOS transistors 19 and 20, and the sensing margin is adversely affected thereby. To salve this problem, not only the voltages of signals .phi.EQL1 and .phi.EQL2 but also those of signals .phi.T1 and .phi.T2 are temporarily boosted by means of the boot-strap circuit.
In some cases, use is made of a semiconductor memory device (such as a DRAM) which employs an internal voltage-generating circuit for generating an internal voltage different from an externally-applied power supply voltage. As such an internal voltage-generating circuit, there is proposed a type which employs a charge pump circuit to generate a boosted voltage at all times. However, in the case where a voltage boosted by the charge pump circuit is used as an internal voltage, a very large capacitance must be connected to the output terminal of the internal voltage generating circuit, so as to absorb the voltage variations during operation.